Pipline Synchronize Buffer (PSB)
- 8 Serial Receivers DS92LV16: 1.2 Gbps 80MHz/16bits
- LVDS Receiver: 64 bits / 40 MHz
- PHASE synchronization: oversampling of parallel input signals
- BC-synchronization: delay circuits for trigger data
- Synchronization to LHC orbit: SIM/SPY memories for each channel
- DAQ: Ringbuffer + FIFO + ROP(state machine)
The Global Calorimeter Trigger (GCT) sends calorimeter trigger objects over fast 1.28 Gbps serial links to three PSB input boards. A PSB board contains 4 Infiniband connectors and 8 DS92LV16 Serializer/Deserializer chips from National Semiconductor to convert the serial data back to 80 MHz, 16 bits wide data streams each carrying data of 2 calorimeter channels that are multiplexed in time. Four calorimeter channels are combined to one quadruplet of 32 bits that means that one Infiniband cable sends data of one quadruplet. A PSB board therefore transmits data of 4 quadruplets to the logic board (GTL) board via the backplane. As the precise arrival time of the data bits is unknown the SYNC chip on the PSB board first samples the input bits 4 times per 12.5 ns tick to find the switching point of the input data. Normally the sample furthest away from the switching time is selected and transmitted.1 Then the SYNC chip delays the trigger data for a programmable time and sends the data as 80 MHz GTL+ signals over the backplane to the GTL board.
Phase selection and delay adjustment is done separately for each 16-bit stream to compensate for any time skew between cables and link chips. The SYNC chip also writes the input data into Ring Buffers and, in parallel, into SPY memories. The Ring Buffers keep data for some time until a L1A signal arrives. Then the Readout Processor (=ROP) moves data belonging to the L1A signal from the Ring Buffer into a Derandomizing Memory and transfers them embedded in a formatted record to the GTFE board. A counter provides the write address for the Ring Buffer and the common BCRES signal resets the counter. The Ring Buffer has been synchronized correctly to the LHC orbit when the first data word of the first bunch crossing is written into the first memory address. The program of the synchronization procedure uses an 8k SPY/SIM memory running in parallel, which accepts the data of a full LHC orbit. It starts the SPY/SIM memory to acquire data of one complete orbit and checks if the data of the first bunch crossing were really written into the first address. If not, the delay for BCRES has to be adjusted accordingly. The BC0-data are flagged by a special sequence in bit 15 of the trigger objects. During data acquisition a private monitoring program can force the SPY memory to run continuously and to stop in case of an L1A signal to check the history of the input data. In test mode, software can load the SPY/SIM memory with test data or simulated input data to send them instead of real data.
Alternatively to using the two serial receiver chips, a PSB module may accept up to 64 parallel LVDS input signals via RJ45 connectors at 40 MHz frequency. Up to 16 bits are reserved for trigger signals of the TOTEM detector to include it into the CMS data acquisition. The parallel data are sampled 4 times per bunch crossing to synchronize them to the local clock signal. Then they are interlaced into an 80-Mhz data stream and transmitted and monitored instead of one of the quadruplets. The synchronization circuit exists for each group of 4 parallel input bits. One dedicated PSB module receives Technical trigger bits as parallel LVDS data and sends them directly to the Final_OR circuit in the Final Decision Logic board (FDL).
Documents and Links
- PSB Module v2
- PSB Chip v2
- VME64 PSB Module v2
- VME Chip of PSB Module v2
- VME64 PSB Module v1012
- VME64 PSB Module v1009