Global Trigger Logic (GTL)

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  • 3 Receiver chips
  • SIM/SPY memories
  • 2 Condition chips EP1S40
  • Algorithm Logic for 128 Algo-bits
  • SIM/SPY memory


On the Global Trigger Logic board (GTL) the three programmable receiver chips accept the 80-MHz trigger data and distribute them to two Condition Chips (COND). Each Condition chip receives all input data, converts them to 40- MHz objects, applies Trigger Conditions and combines the results to up to 64 Algorithms. The Algorithm bits are sent as parallel signals via short flat cables to the Final Decision Logic board (FDL) located in the adjacent slot. As each COND chip receives all trigger bits, all kinds of logical relations between the trigger data could be implemented. Only latency requirements and chip resources restrict the number and type of triggers. But resources could be increased by replacing the Stratix chip EP1S40 by EP1S60 from Altera.1 Algorithms and Conditions

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To implement the Algorithm logic, small predefined VHDL modules are used to compose more complex trigger requirements. Single Particle Templates and Correlation Templates were defined for particle groups (muons, electron/gamma showers, jets). A Single Particle Template (SPT) compares pT or ET against thresholds and checks if the particle is inside an ? and/or f window. For muons the required Isolation-, MIP- and Quality bits are checked in addition, and another pT threshold can be set for isolated muons. A Correlation Template (CT) compares the differences |??| and |?f| between two particles of the same type against thresholds and checks the charge bits for muons. To make a Condition, the required SPT is instantiated four times to apply them to all four particles and - if asked for - also the CT is instantiated as illustrated in Fig. 4. Then the results go to a combinatorial logic circuit to find n out of 4 particles fulfilling the requirements set by the SPTs and CT. Four Conditions types for each particle group are defined: 1s to find one particle out of 4, 2s to find two particles out of 4, 2wsc to find two particles out of 4, correlated in ? and f, 4s to find four particles out of 4 If three objects are required for a particular algorithm the unused sub-condition is set to trivial values (e.g.: ET = 0 GeV, 0 < f < 360 [degree] etc.). Conditions for the total transverse energy, the hadron transverse energy, the missing transverse energy and 12 numbers of jets above different thresholds consist only of comparators. As a last step the Condition bits are combined by a simple combinatorial logic to form a trigger Algorithm. All Condition bits can be used either as trigger or as veto bits. To run the trigger Algorithms, the pT or ET thresholds of existing Conditions are loaded into registers using VMEbus instructions.

When designing a new trigger setup first the Algorithms and Conditions are defined with a Java program (gt_gui ) that runs on all machines. Its output (file def.xml ) is used by a C++ program (gts) that generates the variable VHDL files and a file (vme.xml) that contains addresses and contents for all threshold registers. A second set of thresholds will be defined for lower luminosity periods. The new VHDL files are merged with the fixed code and used by the Quartus software from Altera company to generate a new firmware version. The new firmware must then be loaded to run the new trigger setup. Several firmware versions will be defined to handle data taking as well as calibration and testing periods.

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