Global Trigger Front End (GTFE)

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Overview

Readout of Global Trigger via SLINK connectors to DAQ

  • Event records via Channel Links from GMT, PSBs, FDL, TCS
  • TTCrq receives GPS time
  • SLINK64 DAQ
  • SLINK64 Event Manager
  • Record Formatting:
    • Special FIFO: 16 bits in 64 bits out, sync. reset
    • Crate_ROP: state machine
    • SIM/SPY memory

Description

The FDL and the PSB input boards move all trigger input data into Ring Buffers to store them until a L1Accept signal arrives. The Ring Buffers are implemented as dual port memories inside the FPGA chips and accept the data of one full orbit. On the one side a constant write enable signal writes the trigger data of every bunch crossing into the memory. At the end of an orbit the write address returns to the first location, overwriting old data but keeping the history until a L1A signal arrives after the local latency. The local latency is the time between trigger data passing through and the time when the L1A generated by these data returns. A delayed BCRES signal resets the counter that provides the write address so that data of BC=0 (=BC0 data) are written into location 0. To adjust the BCRES delay correctly, the software can read the SPY memory which runs in parallel to see if the BC0 data were written into the first memory word. On the other side of the Ring Buffer a counter provides the read address which lags behind the write address by the amount of the local latency minus 1 BC, so that a L1A signal reads the correct data words from the BC before until the BC after the event?s BC.

The L1A signal is extended to 3 BC and is applied as a write-enable signal to the Derandomizing Buffer FIFO, which extracts the data of 3 BC per event. When for debugging purposes 5 BC per event are read, the reset signal for the read counter is delayed by 1 BC less and the L1A signal is extended to 5 BC. A readout processor (ROP) designed as a state machine reads the FIFO data of one event and wraps them with format words to create event records. The ROP is located either in the same chip or in a ROP chip if the board contains multiple FPGAs. First the ROP sends a ?read FIFO? command to all FIFOs on the board or in the chip, respectively, to store all data words and their BC-numbers in registers. Then it sends the format words (24-bit event number, board identifier, ?) to the Channel Link and fetches one 16-bit word after the other from the FIFO registers to transmit them also to the Channel Link.

The ROP sends the next ?read FIFO? command to the FIFOs and repeats this procedure for the next two BC data. Finally the ROP sends an ?End_of Record? to the Channel Link and then switches to an ?IDLE? code to keep the link alive. A. Readout board (GTFE) The Global Trigger Readout Board (GTFE = Global Trigger Front End) receives event records via the backplane from the boards in the crate. The readout processor chip (ROP_DAQ) receives event records from the GMT, the FDL, the TCS and all PSB boards, checks the incoming format, combines them to a Global Trigger event record and sends it to the SLINK64 mezzanine board.1 The ROP_EVM chip uses an identical control logic and receives event records from the TCS and FDL boards, adds GPS time - received via a TTCrq mezzanine board - and sends the compiled record via a second SLINK64 to the Event Manager of CMS. Both ROP chips use a Xilinx XC2V2000 FPGA that is mounted on a mezzanine board.2

The GMT and the GT boards use 28-bit Channel Links to send the readout records to the GTFE board. The Channel Link bits 15-0 carry trigger data going into the data FIFOs, bits 23-16 could carry private monitoring data going into separate Monitoring memories, and bits 27-24 carry control bits going to the control logic that detects the begin and end of records. As long as IDLE data arrive the FIFOs remain inactive. The FIFOs are configured so that the output width is 4 times the input width, reordering the trigger data into 64-bit words for the SLINK64 and thus replacing a 4-to-1 multiplexer. A synchronous reset input enables the common L1Reset signal to erase all events in the FIFOs. All FIFOs can keep more than 20 events, are written with 40 MHz and are read with an 80 MHz clock. When the FIFOs become 75% full, a ?Warning? flag is sent to the Trigger Control board to reduce the trigger rate. The capacity of the FIFOs could be doubled by replacing the Xilinx XC2V2000 by a XC2V3000 chip.

Both GTFE chips receive also the common signals L1A, BCRES and Event Counter Reset and create for each event a local Event and BC-number used as reference. The Crate Readout Processor (Crate-ROP) is implemented as a state machine that reads the FIFOs of all active boards. When the first active FIFO has received an ?end-of-record? flag, the ROP applies the standard HEADER word to the SLINK64 and reads all the data of one event on a board, then switches to the next active board FIFO and continues until the last connected board. A comparator circuit checks if the number of events in each channel since the last ?Event Number Reset? signal agrees with the reference number. Any difference is flagged as error bit in the EVENT_STATUS byte. Nevertheless the event transmission continues until the end. Such errors will show up until the synchronization of all boards has been done correctly. Finally, the Crate ROP appends as the last word the Event Status, the updated CRC number and the Event length. During the transmission the CRC and Event status are updated but the Event length is preloaded via VME because it is constant and depends on the number of bunch crossings per event and the boards which contribute data. The Crate-ROP transmits data as long as there are records in the FIFOs and as long as the SLINK64 is ready.

When the SLINK64 returns a ?full? flag, the Crate-ROP simply waits until the SLINK64 becomes ready again. When the off-time is too long the board FIFOs will be filled. When the 75% level is reached, the Crate-ROP sends a ?Warning? flag to the central trigger control system to reduce the trigger rate. When running with an 80-MHz clock, the Crate-ROP transfers a normal GT/GMT event (200 64-bit words) within 2.5 ?s. Even when running only with a 40 MHz clock the event is transferred within 5.0 ?s, thus still exceeding the required 100-kHz event rate. When the SLINK64 for the Event Manager goes into status ?not ready?, the corresponding status signal is sent directly to the TCS board to stop all DAQ-partitions. In both ROP chips a dual port memory spies all event data which are sent to the SLINK64. The SPY memory can also be used to insert test data instead of readout data to test the reliability of the SLINK64. The other side of the SPY memory is accessed by VME-software.

Documents and Links

DAQ

EVM

Hardware