Final Decision Logic (FDL)
- FDL makes FinOR signals
- 128 Algorithms + 64 Technical Triggers
- Rate Counters
- Masks, Veto-mask for TechTrig's
- DAQ: Ringbuffer + FIFO + ROP
- SIM/SPY memories
The "Final Decision Logic" board (FDL) receives 128 ALGORITHM bits from the GTL board and 64 Technical Trigger bits from a dedicated PSB board. Rate counters monitor each trigger bit and pre-scalers reduce the average rate if required. The CMS data acquisition system (DAQ) can be divided into 8 DAQ-partitions to test and calibrate parts of the readout and trigger electronics in parallel. Therefore the FDL board combines all or a subset of the Algorithm and Technical trigger bits to 8 Final_OR signals, one for each DAQpartition, to trigger the DAQ-partitions independently from each other. Mask bits are used to include the Algorithm and Technical Trigger bits into the Final OR gates.
For the Technical Trigger bits there exist also veto-mask bits to inhibit Final_OR signals. The Final_OR signals go to the central trigger control board (TCS) that forwards them - when allowed as Level 1 Accept (L1A) signals to the front-end electronics to read the data of the bunch crossing that has generated the trigger signal and also the data of one bunch crossing before and one after. The FDL board can be read-out like any other front-end electronics module and contains also Ring Buffer memories which store all trigger bits. When an L1A arrives, a Readout Processor (ROP) copies data of the correct bunch crossing into a Derandomizing Buffer, embeds them into a formatted record and sends the record via a Channel Link interface and the backplane to the Global Trigger readout (GTFE) board. As on the other boards, so-called SIM/SPY memories allow either to spy all Algorithm-, Technical Trigger- and Final_OR bits or insert simulated bits for tests. In spy mode the SIM/SPY memories run in parallel to the Ring Buffer so that latency and synchronization to the LHC orbit can be checked and adjusted.
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